As digital integrated circuits function at higher frequencies, the timing of various signals used for clocking data becomes extremely critical. For example, appropriately timed clock signals must be used in order to properly transfer data that is accessed from a digital integrated circuit such as a dynamic random access memory (DRAM). In a read operation, for example, a particular data provided by the DRAM may be valid over a time interval, and as a consequence, must be clocked before the data changes or becomes invalid. As a circuit's frequency of operation increases, it becomes increasingly more difficult to insure that the clock signals are accurately timed for clocking data over a high speed interface.
The timing of clock signals may be influenced, for example, by the conductive path distances these signals must traverse within a printed circuit board. Often, the path a signal travels in a printed circuit board may involve distances that result in delays that vary over time. The electrical characteristics of one or more components on the printed circuit board may have an influence on signals such as timing signals as a function of time. Furthermore, variations in environmental factors such as temperature may have a significant effect on the electrical characteristics of one or more electrical components that influence the behavior of these signals.
When one or more data streams are inappropriately timed to their associated clock signals, a number of errors may result. These timing errors may cause functional or operative failures.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.